// module music (
//     input clk,
//     input rst_n,
//     output speaker
// );

// reg [15:0] counter;

// always @(posedge clk) begin
//     if (rst_n == 1)
//         counter <= 0;
//     else    
//     counter <= counter + 1;
// end

// assign speaker = counter[15];

// endmodule

module music (
    input clk,
    input rst_n,
    output speaker
);

parameter clkdiver = 50000000/400/2;

reg [15:0] counter;

always @(posedge clk) begin
    if (rst_n == 1)
        counter <= 0;
    else if(counter == clkdiver) 
        counter <= 0;  
    else     
    counter <= counter + 1;
end

reg out_speaker;

always @(posedge clk) begin
    if (rst_n == 1)
        out_speaker <= 0;
    else if(counter == 0) 
        out_speaker <= ~ out_speaker;
    else
        begin
            
        end
end

assign speaker = out_speaker;

endmodule
